#archlinux-ports | Logs for 2026-10-08
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[18:30:10] <clover|M> I found a GCC 16 AArch64 wrong-code bug while building Zig 0.17.0. I've isolated it to the RTL ext-DCE optimization pass, and disabling that pass fixes the build.... (full message at <https://matrix.archlinux.org/ircmedia/v1/media/download/AXXxNAHcVV50eFPVPzK_xAgwnZlGmlecF6Ps6mhJCwJTmq9Jb2mcYI7YRiXhF0q5giq2a5bR_IcWS_1QeAKZckBCehZOC0uAAGFyY2hsaW51eC5vcmcvSGdGT2RRb0lYaExNa0ZWaG15amRoY1BZ>)
[18:38:22] <clover|M> not really a big deal, since zig-bin on AUR is multiarch and on 0.17.0 already :)
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